D12320VF25IV Datasheet, PDF (647/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14.2.8 Bit Rate Register (BRR)
Bit
:
7
6
5
Section 14 Serial Communication Interface (SCI)
4
3
2
1
0
Initial value :
1
1
1
1
1
1
1
1
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SMR.
BRR can be read or written to by the CPU at all times.
BRR is initialized to H'FF by a reset and in hardware standby mode. In software standby mode
and module stop mode it retains its previous state.
As baud rate generator control is performed independently for each channel, different values can
be set for each channel.
Table 14.3 shows sample BRR settings in asynchronous mode, and table 14.4 shows sample BRR
settings in synchronous mode.
Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode)
Bit Rate
(bits/s)
110
150
300
600
1200
2400
4800
9600
19200
31250
38400
φ = 2 MHz
φ = 2.097152 MHz
φ = 2.4576 MHz
Error
Error
Error
n
N
(%) n
N
(%) n
N
(%) n
1
141 0.03 1
148 –0.04 1
174 –0.26 1
1
103 0.16 1
108 0.21 1
127 0.00 1
0
207 0.16 0
217 0.21 0
255 0.00 1
0
103 0.16 0
108 0.21 0
127 0.00 0
0
51 0.16 0
54 –0.70 0
63 0.00 0
0
25 0.16 0
26 1.14 0
31 0.00 0
0
12 0.16 0
13 –2.48 0
15 0.00 0
0
6
—0
6
–2.48 0
7
0.00 0
0
2
—0
2
—0
3
0.00 0
0
1
0.00 0
1
—0
1
—0
0
1
—0
1
—0
1
0.00 —
φ = 3 MHz
Error
N
(%)
212 0.03
155 0.16
77 0.16
155 0.16
77 0.16
38 0.16
19 –2.34
9
–2.34
4
–2.34
2
0.00
——
Rev.6.00 Sep. 27, 2007 Page 615 of 1268
REJ09B0220-0600