D12320VF25IV Datasheet, PDF (191/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
Bit 1—Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is
used for an external write cycle or DMAC single address cycle. In the H8S/2321 this bit is
reserved and should only be written with 0.
Bit 1
WDBE
0
1
Description
Write data buffer function not used
Write data buffer function used
(Initial value)
Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT
pin.
Bit 0
WAITE
0
1
Description
Wait input by WAIT pin disabled. WAIT pin can be used as I/O port
Wait input by WAIT pin enabled
(Initial value)
6.2.6 Memory Control Register (MCR)
Bit
:
Initial value :
R/W
:
7
TPC
0
R/W
6
5
4
BE
RCDM
—
0
0
0
R/W
R/W
R/W
3
MXC1
0
R/W
2
MXC0
0
R/W
1
RLW1
0
R/W
0
RLW0
0
R/W
MCR is an 8-bit readable/writable register that selects the DRAM strobe control method, number
of precharge cycles, access mode, address multiplexing shift size, and the number of wait states
inserted during refreshing, when areas 2 to 5 are designated as DRAM interface areas.
MCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Note: In the H8S/2321 this register is reserved and must not be accessed.
Rev.6.00 Sep. 27, 2007 Page 159 of 1268
REJ09B0220-0600