D12320VF25IV Datasheet, PDF (193/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bit 3
MXC1
0
1
Bit 2
MXC0
0
1
0
1
Section 6 Bus Controller
Description
8-bit shift
(Initial value)
• When 8-bit access space is designated: Row address A23 to A8 used
for comparison
• When 16-bit access space is designated: Row address A23 to A9 used
for comparison
9-bit shift
• When 8-bit access space is designated: Row address A23 to A9 used
for comparison
• When 16-bit access space is designated: Row address A23 to A10 used
for comparison
10-bit shift
• When 8-bit access space is designated: Row address A23 to A10 used
for comparison
• When 16-bit access space is designated: Row address A23 to A11 used
for comparison
—
Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the
number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle. This
setting is used for all areas designated as DRAM space. Wait input by the WAIT pin is disabled.
Bit 1
RLW1
0
1
Bit 0
RLW0
0
1
0
1
Description
No wait state inserted
1 wait state inserted
2 wait states inserted
3 wait states inserted
(Initial value)
Rev.6.00 Sep. 27, 2007 Page 161 of 1268
REJ09B0220-0600