D12320VF25IV Datasheet, PDF (177/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6.1.2 Block Diagram
Figure 6.1 shows a block diagram of the bus controller.
CS0 to CS7
Area decoder
External bus control signals
BREQ
BACK
BREQO
ABWCR
ASTCR
BCRH
BCRL
Bus
controller
Section 6 Bus Controller
Internal
address bus
Internal control
signals
Bus mode signal
WAIT
Wait
controller
WCRH
WCRL
External DRAM
signals*
DRAM
controller*
MCR
DRAMCR
RTCNT
RTCOR
Bus arbiter
CPU bus request signal
DTC bus request signal
DMAC bus request signal*
CPU bus acknowledge signal
DTC bus acknowledge signal
DMAC bus acknowledge signal*
Note: * Not supported in the H8S/2321.
Figure 6.1 Block Diagram of Bus Controller
Rev.6.00 Sep. 27, 2007 Page 145 of 1268
REJ09B0220-0600