D12320VF25IV Datasheet, PDF (330/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
Figure 7.34 shows an example of single address transfer using the write data buffer function. In
this example, the CPU program area is in on-chip memory.
DMA DMA
read single
CPU
read
DMA
single
CPU
read
φ
Internal address
Internal read signal
External address
RD
DACK
Figure 7.34 Example of Single Address Transfer Using Write Data Buffer Function
When the write data buffer function is activated, the DMAC recognizes that the bus cycle
concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one
state after the start of the DMA write cycle or single address transfer.
7.5.13 DMAC Multi-Channel Operation
The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table
7.13 summarizes the priority order for DMAC channels.
Table 7.13 DMAC Channel Priority Order
Short Address Mode
Channel 0A
Channel 0B
Channel 1A
Channel 1B
Full Address Mode
Channel 0
Channel 1
Priority
High
Low
Rev.6.00 Sep. 27, 2007 Page 298 of 1268
REJ09B0220-0600