D12320VF25IV Datasheet, PDF (466/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 I/O Ports
Pin
PF3/LWR
Selection Method and Pin Functions
The pin function is switched as shown below according to the operating mode,
bit PF3DDR, and bit LWROD in SYSCR.
Operating
Mode
Modes 4 to 6
Mode 7
LWROD
0
1
—
PF3DDR
Pin function
—
LWR
output pin
0
PF3
input pin
1
PF3
output pin
0
PF3
input pin
1
PF3
output pin
PF2/LCAS^*2/WAIT/ The pin function is switched as shown below according to the combination of
BREQO
the operating mode, and bits RMTS2 to RMTS0^*2, BREQOE, WAITE, ABW5
to ABW2, BREQOPS, WAITPS, and PF2DDR.
Operating Mode
Modes 4 to 6
Mode 7
[DRAM space
0
setting]^*2 ·
[16-bit access
setting]
1
—
[BREQOE ·
0
BREQOPS]
1
—
—
[WAITE ·
0
WAITPS]
1
0
1
—
—
PF2DDR
0
1
0
1
—
—
—
0
1
PF1/BACK
Pin function
PF2
input
pin
PF2
output
pin
WAIT
input
pin*¹
Setting BREQO Setting
pro- output pro-
hibited pin hibited
LCAS
output
pin*²
PF2
input
pin
PF2
output
pin
Notes: 1. When DRAM space is designated for 8-bit access and PF2 is used
as the WAIT input, this pin can be used for WAIT input when all
areas selected as DRAM space are 8-bit space and normal space
other than DRAM space is 16-bit space.
2. The DRAM interface and LCAS are not supported in the H8S/2321.
The pin function is switched as shown below according to the combination of
the operating mode, and bits BRLE and PF1DDR.
Operating
Mode
Modes 4 to 6
Mode 7
BRLE
0
1
—
PF1DDR
Pin function
0
PF1
input pin
1
PF1
output pin
—
BACK
output pin
0
PF1
input pin
1
PF1
output pin
Rev.6.00 Sep. 27, 2007 Page 434 of 1268
REJ09B0220-0600