D12320VF25IV Datasheet, PDF (1215/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

ADCSR—A/D Control/Status Register
Appendix B Internal I/O Registers
H'FF98
A/D Converter
Bit
:
Initial value :
Read/Write :
7
ADF
0
R/(W)^*1
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CKS
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
0
CH0
0
R/W
Channel Select
Note: These bits select the analog input channels.
Ensure that conversion is halted (ADST = 0)
before making a channel selection.
Group Channel
Selection Selection ^{Single Mode Scan Mode}
(SCAN = 0) (SCAN = 1)
CH2 CH1 CH0
0
0
0 AN₀
AN₀
(Initial value)
1 AN₁
1
0 AN₂
1 AN₃
1
0
0 AN₄
1 AN₅
1
0 AN₆
1 AN₇
AN₀, AN₁
AN₀ to AN₂
AN₀ to AN₃
AN₄
AN₄, AN₅
AN₄ to AN₆
AN₄ to AN₇
Clock Select
Note: CKS is used in combination with bit 3 (CKS1)
of ADCR.
See ADCR—A/D Control Register
H'FF99 A/D Converter.
Scan Mode
0 Single mode
1 Scan mode
A/D Start
0 A/D conversion stopped
1 • Single mode: A/D conversion is started. Cleared to 0
automatically when conversion ends
• Scan mode: A/D conversion is started. Conversion continues
sequentially on the selected channels until ADST is cleared to
0 by software, a reset, or transition to standby mode or
module stop mode
A/D Interrupt Enable
0 A/D conversion end interrupt request disabled
A/D End Flag
1 A/D conversion end interrupt request enabled
0 [Clearing conditions]
• When 0 is written to the ADF flag after reading ADF = 1
• When the DMAC^*2 or DTC is activated by an ADI interrupt, and ADDR is read
1 [Setting conditions]
• Single mode: When A/D conversion ends
• Scan mode: When A/D conversion ends on all specified channels
Notes: 1. Can only be written with 0 for flag clearing.
2. The DMAC is not supported in the H8S/2321.
Rev.6.00 Sep. 27, 2007 Page 1183 of 1268
REJ09B0220-0600