D12320VF25IV Datasheet, PDF (293/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
Figure 7.5 illustrates operation in idle mode.
MAR
Transfer
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Figure 7.5 Operation in Idle Mode
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends.
If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC.
The maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission data empty and reception data full interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can be set for channel B only.
When the DMAC is used in single address mode, only channel B can be set.
Rev.6.00 Sep. 27, 2007 Page 261 of 1268
REJ09B0220-0600