D12320VF25IV Datasheet, PDF (337/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
7.7 Usage Notes
DMAC Register Access during Operation: Except for forced termination, the operating
(including transfer waiting state) channel setting should not be changed. The operating channel
setting should only be changed when transfer is disabled.
Also, MAC registers should not be written to in a DMA transfer.
DMAC register reads during operation (including the transfer waiting state) are described below.
(a) DMAC control starts one cycle before the bus cycle, with output of the internal address.
Consequently, MAR is updated in the bus cycle before DMAC transfer.
Figure 7.40 shows an example of the update timing for DMAC registers in dual address
transfer mode.
DMA transfer cycle
DMA read
DMA write
φ
DMA Internal
address
Transfer
source
Transfer
destination
DMA control
Idle
Read
Write
Idle
DMA register
[1]
[2]
operation
DMA last transfer cycle
DMA read
DMA write
DMA
dead
Transfer
source
Transfer
destination
Read
Write
Dead
Idle
[1]
[2']
[3]
[1] Transfer source address register MAR operation (incremented/decremented/fixed)
Transfer counter ETCR operation (decremented)
Block size counter ETCR operation (decremented in block transfer mode)
[2] Transfer destination address register MAR operation (incremented/decremented/fixed)
[2'] Transfer destination address register MAR operation (incremented/decremented/fixed)
Block transfer counter ETCR operation (decremented, in last transfer cycle of a block
in block transfer mode)
[3] Transfer address register MAR restore operation (in block or repeat transfer mode)
Transfer counter ETCR restore (in repeat transfer mode)
Block size counter ETCR restore (in block transfer mode)
Notes: 1. In single address transfer mode, the update timing is the same as [1].
2. The MAR operation is post-incrementing/decrementing of the DMA internal address value.
Figure 7.40 DMAC Register Update Timing
Rev.6.00 Sep. 27, 2007 Page 305 of 1268
REJ09B0220-0600