D12320VF25IV Datasheet, PDF (288/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
Operation in each mode is summarized below.
Sequential Mode: In response to a single transfer request, the specified number of transfers are
carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC
when the specified number of transfers have been completed. One address is specified as 24 bits,
and the other as 16 bits. The transfer direction is programmable.
Idle Mode: In response to a single transfer request, the specified number of transfers are carried
out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the
specified number of transfers have been completed. One address is specified as 24 bits, and the
other as 16 bits. The transfer source address and transfer destination address are fixed. The transfer
direction is programmable.
Repeat Mode: In response to a single transfer request, the specified number of transfers are
carried out, one byte or one word at a time. When the specified number of transfers have been
completed, the addresses and transfer counter are restored to their original settings, and operation
is continued. No interrupt request is sent to the CPU or DTC. One address is specified as 24 bits,
and the other as 16 bits. The transfer direction is programmable.
Single Address Mode: In response to a single transfer request, the specified number of transfers
are carried out between external memory and an external device, one byte or one word at a time.
Unlike dual address mode, source and destination accesses are performed in parallel. Therefore,
either the source or the destination is an external device which can be accessed with a strobe alone,
using the DACK pin. One address is specified as 24 bits, and for the other, the pin is set
automatically. The transfer direction is programmable.
Sequential mode, idle mode, and repeat mode can also be specified for single address mode.
Normal Mode
• Auto-request
By means of register settings only, the DMAC is activated, and transfer continues until the
specified number of transfers have been completed. An interrupt request can be sent to the
CPU or DTC when transfer is completed. Both addresses are specified as 24 bits.
⎯ Cycle steal mode
The bus is released to another bus master after each byte or word transfer.
⎯ Burst mode
⎯ The bus is held and transfer continued until the specified number of transfers have been
completed.
Rev.6.00 Sep. 27, 2007 Page 256 of 1268
REJ09B0220-0600