D12320VF25IV Datasheet, PDF (725/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 Smart Card Interface
Data Transfer Operation by DMAC^* or DTC: In smart card mode, as with the normal SCI,
transfer can be carried out using the DMAC* or DTC. In a transmit operation, the TDRE flag is
also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the
TXI request is designated beforehand as a DMAC* or DTC activation source, the DMAC* or
DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. The
TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the
DMAC* or DTC. In the event of an error, the SCI retransmits the same data automatically. The
TEND flag remains cleared to 0 during this time, and the DMAC* is not activated. Thus, the
number of bytes specified by the SCI and DMAC* are transmitted automatically even in
retransmission following an error. However, the ERS flag is not cleared automatically when an
error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be
generated in the event of an error, and the ERS flag will be cleared.
When performing transfer using the DMAC* or DTC, it is essential to set and enable the DMAC*
or DTC before carrying out SCI setting. For details of the DMAC* and DTC setting procedures,
see section 7, DMA Controller*, and section 8, Data Transfer Controller.
In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to
1. If the RXI request is designated beforehand as a DMAC* or DTC activation source, the
DMAC* or DTC will be activated by the RXI request, and transfer of the receive data will be
carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the
DMAC* or DTC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently,
the DMAC* or DTC is not activated, but instead, an ERI interrupt request is sent to the CPU.
Therefore, the error flag should be cleared.
Notes: For details of operation in block transfer mode, see section 14.4, SCI Interrupts.
* The DMAC is not supported in the H8S/2321.
Rev.6.00 Sep. 27, 2007 Page 693 of 1268
REJ09B0220-0600