D12320VF25IV Datasheet, PDF (259/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
7.2.4 DMA Control Register (DMACR)
Bit
:
Initial value :
R/W
:
7
DTSZ
0
R/W
6
DTID5
0
R/W
5
RPE
0
R/W
4
DTDIR
0
R/W
3
DTF3
0
R/W
2
DTF2
0
R/W
1
DTF1
0
R/W
0
DTF0
0
R/W
DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel.
DMACR is initialized to H'00 by a reset, and in standby mode.
Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.
Bit 7
DTSZ
0
1
Description
Byte-size transfer
Word-size transfer
(Initial value)
Bit 6—Data Transfer Increment/Decrement (DTID): Selects incrementing or decrementing of
MAR after every data transfer in sequential mode or repeat mode.
In idle mode, MAR is neither incremented nor decremented.
Bit 6
DTID
0
1
Description
MAR is incremented after a data transfer
• When DTSZ = 0, MAR is incremented by 1 after a transfer
• When DTSZ = 1, MAR is incremented by 2 after a transfer
MAR is decremented after a data transfer
• When DTSZ = 0, MAR is decremented by 1 after a transfer
• When DTSZ = 1, MAR is decremented by 2 after a transfer
(Initial value)
Rev.6.00 Sep. 27, 2007 Page 227 of 1268
REJ09B0220-0600