D12320VF25IV Datasheet, PDF (1139/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
BCRH—Bus Control Register H
H'FED4
Bus Controller
Bit
:
Initial value :
Read/Write :
7
ICIS1
1
R/W
6
ICIS0
1
R/W
5
4
3
2
BRSTRM BRSTS1 BRSTS0 RMTS2
0
1
0
0
R/W R/W R/W R/W
1
RMTS1
0
R/W
0
RMTS0
0
R/W
RAM Type Select
RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2
0
0
0
Normal space
1
Normal space
DRAM
space
1
0 Normal space DRAM space
1
DRAM space
1
——
—
Notes: 1. When areas selected in DRAM
space are all 8-bit space, the PF2
pin can be used as an I/O port,
BREQO, or WAIT. When PF2 is
used as the WAIT pin in the
H8S/2323, normal space other than
DRAM space should be designated
as 16-bit-bus space. RAS down
mode cannot be used when this
setting is made. Sample settings
are shown below.
RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2
0
0
0
Normal space
1
Normal space DRAM space
(16-bit bus)
(8-bit bus)
1
0
Normal space
(16-bit bus)
DRAM space
(8-bit bus)
1
DRAM space
(8-bit bus)
2. In the H8S/2321 these bits are reserved
and should only be written with 0.
Burst Cycle Select 0
0 Max. 4 words in burst access
1 Max. 8 words in burst access
Burst Cycle Select 1
0 Burst cycle comprises 1 state
1 Burst cycle comprises 2 states
Area 0 Burst ROM Enable
0 Basic bus interface
1 Burst ROM interface
Idle Cycle Insert 0
0 Idle cycle not inserted in case of successive external read and external write cycles
1 Idle cycle inserted in case of successive external read and external write cycles
Idle Cycle Insert 1
0 Idle cycle not inserted in case of successive external read cycles in different areas
1 Idle cycle inserted in case of successive external read cycles in different areas
Rev.6.00 Sep. 27, 2007 Page 1107 of 1268
REJ09B0220-0600