D12320VF25IV Datasheet, PDF (449/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 I/O Ports
9.11.2 Register Configuration
Table 9.20 shows the port D register configuration.
Table 9.20 Port D Registers
Name
Abbreviation R/W
Port D data direction register
PDDDR
W
Port D data register
PDDR
R/W
Port D register
PORTD
R
Port D MOS pull-up control register PDPCR
R/W
Note: * Lower 16 bits of the address.
Initial Value
H'00
H'00
Undefined
H'00
Address^*
H'FEBC
H'FF6C
H'FF5C
H'FF73
Port D Data Direction Register (PDDDR)
Bit
:
7
6
5
4
3
2
1
0
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
:W
W
W
W
W
W
W
W
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.
PDDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
• Modes 4 to 6
The input/output direction specification by PDDDR is ignored, and port D is automatically
designated for data I/O.
• Mode 7
Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing
the bit to 0 makes the pin an input port.
Rev.6.00 Sep. 27, 2007 Page 417 of 1268
REJ09B0220-0600