D12320VF25IV Datasheet, PDF (428/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 I/O Ports
Port A Data Register (PADR)
Bit
:
Initial value :
R/W
:
7
PA7DR
0
R/W
6
PA6DR
0
R/W
5
PA5DR
0
R/W
4
PA4DR
0
R/W
3
PA3DR
0
R/W
2
PA2DR
0
R/W
1
PA1DR
0
R/W
0
PA0DR
0
R/W
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA₇ to
PA₀).
PADR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Port A Register (PORTA)
Bit
:
7
6
5
4
3
2
1
0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Initial value : —^*
—^*
—^*
—^*
—^*
—^*
—^*
—^*
R/W
:R
R
R
R
R
R
R
R
Note: * Determined by state of pins PA7 to PA0.
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port A pins (PA₇ to PA₀) must always be performed on PADR.
If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A
read is performed while PADDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTA contents are determined by the pin states, as
PADDR and PADR are initialized. PORTA retains its prior state in software standby mode.
Rev.6.00 Sep. 27, 2007 Page 396 of 1268
REJ09B0220-0600