D12320VF25IV Datasheet, PDF (231/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.6.2 When DDS = 0
When DRAM space is accessed in DMAC single address mode, full access (normal access) is
always performed. The DACK output goes low from the T_r state in the case of the DRAM
interface.
In modes other than DMAC single address mode, burst access can be used when accessing DRAM
space.
Figure 6.29 shows the DACK output timing for the DRAM interface when DDS = 0.
φ
A₂₃ to A₀
CSn (RAS)
CAS (UCAS)
LCAS (LCAS)
Read
HWR (WE)
D₁₅ to D₀
Write
HWR (WE)
D₁₅ to D₀
DACK
T_p
T_r
T_c1
T_c2
Row
Column
Note: n = 2 to 5
Figure 6.29 DACK Output Timing when DDS = 0 (Example of DRAM Access)
Rev.6.00 Sep. 27, 2007 Page 199 of 1268
REJ09B0220-0600