D12320VF25IV Datasheet, PDF (159/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

5.4 Interrupt Operation
Section 5 Interrupt Controller
5.4.1 Interrupt Control Modes and Interrupt Operation
Interrupt operations in the chip differ depending on the interrupt control mode.
NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In
the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for
each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt
sources for which the enable bits are set to 1 are controlled by the interrupt controller.
Table 5.5 shows the interrupt control modes.
The interrupt controller performs interrupt control according to the interrupt control mode set by
the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated
by the I bit in the CPU’s CCR, and bits I2 to I0 in EXR.
Table 5.5 Interrupt Control Modes
Interrupt
Control Mode
0
—
2
—
SYSCR
INTM1 INTM0
0
0
Priority Setting
Registers
—
Interrupt
Mask Bits
I
1
—
1
0
IPR
—
I2 to I0
1
—
—
Description
Interrupt mask control is
performed by the I bit.
Setting prohibited
8-level interrupt mask control
is performed by bits I2 to I0.
8 priority levels can be set
with IPR.
Setting prohibited
Rev.6.00 Sep. 27, 2007 Page 127 of 1268
REJ09B0220-0600