D12320VF25IV Datasheet, PDF (16/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

5.6 DTC and DMAC Activation by Interrupt ......................................................................... 139
5.6.1 Overview.............................................................................................................. 139
5.6.2 Block Diagram ..................................................................................................... 140
5.6.3 Operation ............................................................................................................. 141
Section 6 Bus Controller....................................................................................143
6.1 Overview........................................................................................................................... 143
6.1.1 Features................................................................................................................ 143
6.1.2 Block Diagram ..................................................................................................... 145
6.1.3 Pin Configuration................................................................................................. 146
6.1.4 Register Configuration......................................................................................... 148
6.2 Register Descriptions ........................................................................................................ 149
6.2.1 Bus Width Control Register (ABWCR)............................................................... 149
6.2.2 Access State Control Register (ASTCR) ............................................................. 150
6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 151
6.2.4 Bus Control Register H (BCRH) ......................................................................... 154
6.2.5 Bus Control Register L (BCRL) .......................................................................... 157
6.2.6 Memory Control Register (MCR)........................................................................ 159
6.2.7 DRAM Control Register (DRAMCR) ................................................................. 162
6.2.8 Refresh Timer Counter (RTCNT)........................................................................ 164
6.2.9 Refresh Time Constant Register (RTCOR) ......................................................... 164
6.3 Overview of Bus Control .................................................................................................. 165
6.3.1 Area Partitioning.................................................................................................. 165
6.3.2 Bus Specifications................................................................................................ 166
6.3.3 Memory Interfaces ............................................................................................... 167
6.3.4 Advanced Mode ................................................................................................... 168
6.3.5 Chip Select Signals .............................................................................................. 169
6.4 Basic Bus Interface ........................................................................................................... 170
6.4.1 Overview.............................................................................................................. 170
6.4.2 Data Size and Data Alignment............................................................................. 170
6.4.3 Valid Strobes........................................................................................................ 172
6.4.4 Basic Timing........................................................................................................ 173
6.4.5 Wait Control ........................................................................................................ 181
6.5 DRAM Interface (Not supported in the H8S/2321) .......................................................... 183
6.5.1 Overview.............................................................................................................. 183
6.5.2 Setting DRAM Space........................................................................................... 183
6.5.3 Address Multiplexing........................................................................................... 184
6.5.4 Data Bus............................................................................................................... 184
6.5.5 Pins Used for DRAM Interface............................................................................ 185
6.5.6 Basic Timing........................................................................................................ 186
Rev.6.00 Sep. 27, 2007 Page xiv of xxx
REJ09B0220-0600