D12320VF25IV Datasheet, PDF (907/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 ROM
• The RxD1 and TxD1 pins should be pulled up on the board.
• Before branching to the programming control program (RAM area H'FFE400 to H'FFFBFF),
the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing
the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The
transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1, P31DR = 1).
• The contents of the CPU’s internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the programming control program.
In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area
must be specified for use by the programming control program.
Initial settings must also be made for the other on-chip registers.
• Boot mode can be entered by making the pin settings shown in table 19.51 and executing a
reset-start.
Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting
the mode pins, and executing reset release*¹. Boot mode can also be cleared by a WDT
overflow reset.
Do not change the mode pin input levels in boot mode. Do not make the FWE pin low level
while a boot program is executing, or while programming or erasing flash memory*².
• If the mode pin input levels are changed (for example, from low to high) during a reset, the
state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR)
will change according to the change in the microcomputer’s operating mode*³.
Therefore, care must be taken to make pin settings to prevent these pins from becoming output
signal pins during a reset, or to prevent collision with signals outside the microcomputer.
Notes: 1. Input to the mode pins and FWE pin must satisfy the mode programming setup time
(t_MDS = 200 ns) requirement with regard to the reset release timing, as shown in figures
19.86 to 19.88.
2. Refer to section 19.30, Flash Memory Programming and Erasing Precautions, for
precautions regarding applying signals to and releasing the FWE pin.
3. See section 9, I/O Ports.
Rev.6.00 Sep. 27, 2007 Page 875 of 1268
REJ09B0220-0600