D12320VF25IV Datasheet, PDF (621/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Writing 0 to WOVF bit
15
Address: H'FFBE
H'A5
Section 13 Watchdog Timer
87
0
H'00
Writing to RSTE bit
15
Address: H'FFBE
H'5A
87
0
Write data
Figure 13.3 Writing to RSTCSR
Reading TCNT, TCSR, and RSTCSR: These registers are read in the same way as other
registers. The read addresses are H'FFBC for TCSR, H'FFBD for TCNT, and H'FFBF for
RSTCSR.
13.3 Operation
13.3.1 Operation in Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent
TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflow occurs.
This ensures that TCNT does not overflow while the system is operating normally. If TCNT
overflows without being rewritten because of a system crash or other error, the WDTOVF signal*
is output. This is shown in figure 13.4. This WDTOVF signal* can be used to reset the system.
The WDTOVF signal* is output for 132 states when RSTE = 1, and for 130 states when RSTE =
0.
If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the chip
internally is generated at the same time as the WDTOVF signal*. The internal reset signal is
output for 518 states.
If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a
WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.
Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions.
Rev.6.00 Sep. 27, 2007 Page 589 of 1268
REJ09B0220-0600