D12320VF25IV Datasheet, PDF (470/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 I/O Ports
Port Function Control Register 2 (PFCR2)
Bit
:
7
6
5
4
3
2
1
0
WAITPS BREQOPS CS167E CS25E ASOD
—
—
—
Initial value :
0
0
1
1
0
0
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R
R
R
PFCR2 is an 8-bit readable/writable register that performs I/O port control. PFCR2 is initialized to
H'30 by a reset, and in hardware standby mode.
Bit 7—WAIT Pin Select (WAITPS): Selects the WAIT input pin. For details, see section 9.6,
Port 5.
Bit 6—BREQO Pin Select (BREQOPS): Selects the BREQO output pin. For details, see section
9.6, Port 5.
Bit 5—CS167 Enable (CS167E): Enables or disables CS₁, CS₆, and CS₇ output. Change the
CS167E setting only when the DDR bits are cleared to 0.
Bit 5
CS167E
0
1
Description
CS1, CS6, and CS7 output disabled (can be used as I/O ports)
CS1, CS6, and CS7 output enabled
(Initial value)
Bit 4—CS25 Enable (CS25E): Enables or disables CS₂, CS₃, CS₄, and CS₅ output. Change the
CS25E setting only when the DDR bits are cleared to 0.
Bit 4
CS25E
0
1
Description
CS2, CS3, CS4, and CS5 output disabled (can be used as I/O ports)
CS2, CS3, CS4, and CS5 output enabled
(Initial value)
Bit 3—AS Output Disable (ASOD): Enables or disables AS output. For details, see section 9.13,
Port F.
Bits 2 to 0—Reserved: These bits are always read as 0.
Rev.6.00 Sep. 27, 2007 Page 438 of 1268
REJ09B0220-0600