D12320VF25IV Datasheet, PDF (245/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.10.5 Usage Note
Do not set MSTPCR to H'FFFF or H'EFFF, since the external bus release function will halt if a
transition is made to sleep mode when either of these settings has been made.
6.11 Bus Arbitration
6.11.1 Overview
The chip has a bus arbiter that arbitrates bus master operations.
There are three bus masters, the CPU, DTC, and DMAC*, which perform read/write operations
when they have possession of the bus. Each bus master requests the bus by means of a bus request
signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by
means of a bus request acknowledge signal. The selected bus master then takes possession of the
bus and begins its operation.
Note: * The DMAC is not supported in the H8S/2321.
6.11.2 Operation
The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus
request acknowledge signal to the bus master making the request. If there are bus requests from
more than one bus master, the bus request acknowledge signal is sent to the one with the highest
priority. When a bus master receives the bus request acknowledge signal, it takes possession of the
bus until that signal is canceled.
The order of priority of the bus masters is as follows:
(High) DMAC* > DTC > CPU (Low)
An internal bus access by an internal bus master, external bus release, and refreshing*, can be
executed in parallel.
In the event of simultaneous external bus release request, refresh request*, and internal bus master
external access request generation, the order of priority is as follows:
(High) Refresh* > External bus release (Low)
(High) External bus release > Internal bus master external access (Low)
Rev.6.00 Sep. 27, 2007 Page 213 of 1268
REJ09B0220-0600