D12320VF25IV Datasheet, PDF (169/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

5.5 Usage Notes
Section 5 Interrupt Controller
5.5.1 Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or
MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will
still be enabled on completion of the instruction, and so interrupt exception handling for that
interrupt will be executed on completion of the instruction. However, if there is an interrupt
request of higher priority than that interrupt, interrupt exception handling will be executed for the
higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared.
Figure 5.8 shows an example in which the TGIEA bit in the TPU’s TIER0 register is cleared to 0.
TIER0 write cycle by CPU
TGI0A exception handling
φ
Internal
address bus
Internal
write signal
TIER0 address
TGIEA
TGFA
TGI0A
interrupt signal
Figure 5.8 Contention between Interrupt Generation and Disabling
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
Rev.6.00 Sep. 27, 2007 Page 137 of 1268
REJ09B0220-0600