D12320VF25IV Datasheet, PDF (1140/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
BCRL—Bus Control Register L
H'FED5
Bus Controller
Bit
:
Initial value :
Read/Write :
7
BRLE
0
R/W
6
BREQOE
0
R/W
5
EAE
1
R/W
4
—
1
R/W
3
DDS
1
R/W
2
1
0
— WDBE WAITE
1
0
0
R/W
R/W
R/W
WAIT Pin Enable
0 Wait input by WAIT
pin^* disabled
1 Wait input by WAIT
pin^* enabled
Note: * The WAIT input pin
can be switched
between PF₂ and
P5₃ by means of
WAITPS.
Write Data Buffer Enable
0 Write data buffer function
not used
1 Write data buffer function
used
Reserved
Only 1 should be written to this bit
DACK Timing Select
0 When DMAC single address transfer is performed in
DRAM space, full access is always executed. DACK
signal goes low from Tr or T1 cycle
1 Burst access is possible when DMAC single address
transfer is performed in DRAM space. DACK signal
goes low from Tc1 or T2 cycle
Note: In the H8S/2321 this bit is reserved and should only
Reserved
be written with 1.
Only 1 should be written to this bit
External Addresses H'010000 to H'03FFFF Enable
0 • In the H8S/2329B, H8S/2328^*3, and H8S/2326, addresses H'010000 to
H'03FFFF^*2 are on-chip ROM
• In the H8S/2327, addresses H'010000 to H'01FFFF are on-chip ROM,
and addresses H'020000 to H'03FFFF are a reserved area^*1
• In the H8S/2323, addresses H'010000 to H'03FFFF are a reserved area^*1
1 Addresses H'010000 to H'03FFFF^*2 are external addresses
in external expanded mode or reserved area^*2 in single-chip mode
Notes: 1. Do not access a reserved area.
2. Address H'010000 to H'03FFFF in the H8S/2328.
Address H'010000 to H'05FFFF in the H8S/2329B.
Address H'010000 to H'07FFFF in the H8S/2326.
3. H8S/2328B in flash memory version.
BREQO Pin Enable
0 BREQO output disabled
1 BREQO^* output enabled
Note: * The BREQO output pin can be switched between
PF₂ and P5₃ by means of BREQOPS.
Bus Release Enable
0 External bus release disabled
1 External bus release enabled
Rev.6.00 Sep. 27, 2007 Page 1108 of 1268
REJ09B0220-0600