D12320VF25IV Datasheet, PDF (786/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 ROM
19.5.3 Erase Block Register 1 (EBR1)
Bit
:
7
6
5
4
3
2
1
0
EBR1
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, and the SWE
bit in FLMCR1 is not set. When a bit in EBR1 is set, the corresponding block can be erased. Other
blocks are erase-protected. Set only one bit in EBR1 and EBR2 together (setting more than one bit
will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash memory is disabled, a
read will return H'00 and writes are invalid.
The flash memory block configuration is shown in table 19.7.
19.5.4 Erase Block Registers 2 (EBR2)
Bit
:
7
EBR2
—
Initial value :
0
R/W
:—
6
5
4
3
2
1
0
—
EB13 EB12 EB11 EB10 EB9
EB8
0
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
R/W
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, and the SWE
bit in FLMCR1 is not set. When a bit in EBR2 is set, the corresponding block can be erased. Other
blocks are erase-protected. Set only one bit in EBR2 and EBR1 together (setting more than one bit
will automatically clear all EBR1 and EBR2 bits to 0). Bits 7 and 6 are reserved: they are always
read as 0 and cannot be modified. When on-chip flash memory is disabled, a read will return H'00,
and writes are invalid.
The flash memory block configuration is shown in table 19.7.
Rev.6.00 Sep. 27, 2007 Page 754 of 1268
REJ09B0220-0600