D12320VF25IV Datasheet, PDF (463/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Port Function Control Register 2 (PFCR2)
Bit
:
7
6
5
WAITPS BREQOPS CS167E
Initial value :
0
0
1
R/W
: R/W
R/W
R/W
4
CS25E
1
R/W
3
ASOD
0
R/W
Section 9 I/O Ports
2
1
0
—
—
—
0
0
0
R
R
R
PFCR2 is an 8-bit readable/writable register that performs I/O port control. PFCR2 is initialized to
H'30 by a reset, and in hardware standby mode.
Bit 7—WAIT Pin Select (WAITPS): Selects the WAIT input pin. Set the WAITPS bit before
setting the DDR bit clear to 0 and the WAITE bit in BCRL to 1.
Bit 7
WAITPS
0
1
Description
WAIT input is pin PF2
WAIT input is pin P53
(Initial value)
Bit 6—BREQO Pin Select (BREQOPS): Selects the BREQO output pin. Set the BREQOPS bit
before setting the BREQOE bit in BCRL to 1.
Bit 6
BREQOPS
0
1
Description
BREQO output is pin PF2
BREQO output is pin P53
(Initial value)
Bit 5—CS167 Enable (CS167E): Enables or disables CS₁, CS₆, and CS₇ output. For details, see
section 9.7, Port 6, and section 9.14, Port G.
Bit 4—CS25 Enable (CS25E): Enables or disables CS₂, CS₃, CS₄, and CS₅ output. For details,
see section 9.7, Port 6, and section 9.14, Port G.
Bit 3—AS Output Disable (ASOD): Enables or disables AS output. This bit is valid in modes 4
to 6.
Bit 3
ASOD
0
1
Description
PF6 is used as AS output pin
(Initial value)
PF6 is designated as I/O port, and does not function as AS output pin
Rev.6.00 Sep. 27, 2007 Page 431 of 1268
REJ09B0220-0600