D12320VF25IV Datasheet, PDF (352/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 Data Transfer Controller
8.2.8 DTC Vector Register (DTVECR)
Bit
:
7
6
5
4
3
2
1
0
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/(W) R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^*
Note: * Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by
software, and sets a vector number for the software activation interrupt.
DTVECR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by
software.
Bit 7
SWDTE
0
1
Description
DTC software activation is disabled
(Initial value)
[Clearing conditions]
• When the DISEL bit is 0 and the specified number of transfers have not ended
• When 0 is written after a software activation data-transfer-complete interrupt is
issued to the CPU
DTC software activation is enabled
[Holding conditions]
• When the DISEL bit is 1 and data transfer has ended
• When the specified number of transfers have ended
• During data transfer due to software activation
Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits
specify a vector number for DTC software activation.
The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit left-
shift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420.
Rev.6.00 Sep. 27, 2007 Page 320 of 1268
REJ09B0220-0600