D12320VF25IV Datasheet, PDF (602/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 8-Bit Timers
12.3.3 Timing of TCNT External Reset
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 12.7
shows the timing of this operation.
φ
External reset
input pin
Clear signal
TCNT
N–1
N
H'00
Figure 12.7 Timing of Clearance by External Reset
12.3.4 Timing of Overflow Flag (OVF) Setting
The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 12.8
shows the timing of this operation.
φ
TCNT
Overflow signal
H'FF
H'00
OVF
Figure 12.8 Timing of OVF Setting
Rev.6.00 Sep. 27, 2007 Page 570 of 1268
REJ09B0220-0600