D12320VF25IV Datasheet, PDF (327/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the
DREQ pin is selected to 1.
Figure 7.31 shows an example of DREQ pin falling edge activated single address mode transfer.
φ
DREQ
Address bus
DACK
Bus release DMA single Bus release DMA single Bus release
Transfer source/
destination
Transfer source/
destination
DMA control ^Idle
Single
Idle
Single
Idle
Channel
Request
Minimum of
2 cycles
Request clear
period
Request
Minimum of
2 cycles
Request clear
period
[1] [2] [3]
[4] [5] [6]
[7]
Acceptance resumes
Acceptance resumes
[1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the single
cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and
the request is held.)
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.31 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA single cycle ends, acceptance
Rev.6.00 Sep. 27, 2007 Page 295 of 1268
REJ09B0220-0600