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Section 7 DMA Controller (Not Supported in the H8S/2321)
7.6 Interrupts
The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.14
shows the interrupt sources and their priority order.
Table 7.14 Interrupt Source Priority Order
Interrupt
Name
DEND0A
DEND0B
DEND1A
DEND1B
Interrupt Source
Short Address Mode
Full Address Mode
Interrupt due to end of
transfer on channel 0A
Interrupt due to end of
transfer on channel 0
Interrupt due to end of
transfer on channel 0B
Interrupt due to break in
transfer on channel 0
Interrupt due to end of
transfer on channel 1A
Interrupt due to end of
transfer on channel 1
Interrupt due to end of
transfer on channel 1B
Interrupt due to break in
transfer on channel 1
Interrupt
Priority Order
High
Low
Enabling or disabling of each interrupt source is set by means of the DTIE bit for the
corresponding channel in DMABCR, and interrupts from each source are sent to the interrupt
controller independently.
The relative priority of transfer end interrupts on each channel is decided by the interrupt
controller, as shown in table 7.14.
Figure 7.39 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is
always generated when the DTIE bit is set to 1 while the DTE bit is cleared to 0.
DTE/
DTME
DTIE
Transfer end/transfer
break interrupt
Figure 7.39 Block Diagram of Transfer End/Transfer Break Interrupt
In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to 0
while the DTIEB bit is set to 1.
In both short address mode and full address mode, DMABCR should be set so as to prevent the
occurrence of a combination that constitutes a condition for interrupt generation during setting.
Rev.6.00 Sep. 27, 2007 Page 304 of 1268
REJ09B0220-0600