D12320VF25IV Datasheet, PDF (552/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Timer Pulse Unit (TPU)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC or DMAC* is activated, the flag is cleared automatically. Figure 10.46
shows the timing for status flag clearing by the CPU, and figure 10.47 shows the timing for status
flag clearing by the DTC or DMAC*.
Note: * The DMAC is not supported in the H8S/2321.
TSR write cycle
T₁
T₂
φ
Address
TSR address
Write signal
Status flag
Interrupt
request
signal
Figure 10.46 Timing for Status Flag Clearing by CPU
DTC/DMAC*
read cycle
T₁
T₂
DTC/DMAC*
write cycle
T₁
T₂
φ
Address
Status flag
Source address
Destination
address
Interrupt
request
signal
Note: * The DMAC is not supported in the H8S/2321.
Figure 10.47 Timing for Status Flag Clearing by DTC/DMAC Activation
Rev.6.00 Sep. 27, 2007 Page 520 of 1268
REJ09B0220-0600