D12320VF25IV Datasheet, PDF (689/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 14 Serial Communication Interface (SCI)
Table 14.12 SCI Interrupt Sources
Interrupt
Channel Source Description
DTC
DMAC^*2
Activation Activation Priority^*1
0
ERI
Interrupt due to receive error
Not
Not
High
(ORER, FER, or PER)
possible possible
RXI
Interrupt due to receive data full
Possible Possible
state (RDRF)
TXI
Interrupt due to transmit data empty Possible Possible
state (TDRE)
TEI
Interrupt due to transmission end Not
Not
(TEND)
possible possible
1
ERI
Interrupt due to receive error
Not
Not
(ORER, FER, or PER)
possible possible
RXI
Interrupt due to receive data full
Possible Possible
state (RDRF)
TXI
Interrupt due to transmit data empty Possible Possible
state (TDRE)
TEI
Interrupt due to transmission end Not
Not
(TEND)
possible possible
2
ERI
Interrupt due to receive error
Not
Not
(ORER, FER, or PER)
possible possible
RXI
Interrupt due to receive data full
Possible Not
state (RDRF)
possible
TXI
Interrupt due to transmit data empty Possible Not
state (TDRE)
possible
TEI
Interrupt due to transmission end Not
Not
(TEND)
possible possible Low
Notes: 1. This table shows the initial state immediate after a reset. Relative priorities among
channels can be changed by the interrupt controller.
2. The DMAC is not supported in the H8S/2321.
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The
TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a
TXI interrupt are requested simultaneously, the TXI interrupt may be accepted first, with the result
that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be accepted in this
case.
Rev.6.00 Sep. 27, 2007 Page 657 of 1268
REJ09B0220-0600