D12320VF25IV Datasheet, PDF (224/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.5.10 Burst Operation
With DRAM, in addition to full access (normal access) in which data is accessed by outputting a
row address for each access, a fast page mode is also provided which can be used when making a
number of consecutive accesses to the same row address. This mode enables fast (burst) access of
data by simply changing the column address after the row address has been output. Burst access
can be selected by setting the BE bit in MCR to 1.
Burst Access (Fast Page Mode) Operation Timing: Figure 6.20 shows the operation timing for
burst access. When there are consecutive access cycles for DRAM space, the CAS signal and
column address output cycles (two states) continue as long as the row address is the same for
consecutive access cycles. The row address used for the comparison is set with bits MXC1 and
MXC0 in MCR.
T_p
T_r
T_c1
T_c2
T_c1
T_c2
φ
A₂₃ to A₀
Row
Column 1
Column 2
CSn (RAS)
CAS, LCAS
Read
HWR (WE)
D₁₅ to D₀
Write
HWR (WE)
D₁₅ to D₀
Note: n = 2 to 5
Figure 6.20 Operation Timing in Fast Page Mode
The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion
method and timing are the same as for full access. For details, see section 6.5.8, Wait Control.
Rev.6.00 Sep. 27, 2007 Page 192 of 1268
REJ09B0220-0600