D12320VF25IV Datasheet, PDF (190/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'03FFFF*² are
to be internal addresses or external addresses.
Bit 5
0
1
Description
H8S/2329B, H8S/2328^*3,
H8S/2326
H8S/2327
H8S/2323
On-chip ROM
Addresses H'010000 to
H'01FFFF are on-chip
ROM or address H'020000
to H'03FFFF are reserved
area^*1
Reserved area^*1
Addresses H'010000 to H'03FFFF^*2 are external addresses in external expanded mode
or reserved area^*1 in single-chip mode
(Initial value)
Notes: 1. Do not access a reserved area.
2. Addresses H'010000 to H'05FFFF in the H8S/2329B.
Addresses H'010000 to H'07FFFF in the H8S/2326.
3. H8S/2328B in F-ZTAT version.
Bit 4—Reserved: Only 1 should be written to this bit.
Bit 3—DACK Timing Select (DDS): Selects the DMAC single address transfer bus timing for
the DRAM interface. In the H8S/2321 this bit is reserved and should only be written with 1.
Bit 3
DDS
0
1
Description
When DMAC single address transfer is performed in DRAM space, full access is
always executed
DACK signal goes low from Tr or T1 cycle
Burst access is possible when DMAC single address transfer is performed in DRAM
space
DACK signal goes low from Tc1 or T2 cycle
(Initial value)
Bit 2—Reserved: Only 1 should be written to this bit.
Rev.6.00 Sep. 27, 2007 Page 158 of 1268
REJ09B0220-0600