D12320VF25IV Datasheet, PDF (283/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bit
:
7
—
Initial value :
0
R/W
:—
Section 7 DMA Controller (Not Supported in the H8S/2321)
6
5
4
3
2
1
0
—
—
—
WE1B WE1A WE0B WE0A
0
0
0
0
0
0
0
—
—
—
R/W
R/W
R/W
R/W
DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to
DMACR, DMABCR, and DMATCR by the DTC.
DMAWER is initialized to H'00 by a reset, and in hardware standby mode.
Bits 7 to 4—Reserved: Read-only bits, always read as 0.
Bit 3—Write Enable 1B (WE1B): Enables or disables writes to all bits in DMACR1B, bits 11, 7,
and 3 in DMABCR, and bit 5 in DMATCR, by the DTC.
Bit 3
WE1B
0
1
Description
Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR
are disabled
(Initial value)
Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR
are enabled
Bit 2—Write Enable 1A (WE1A): Enables or disables writes to all bits in DMACR1A, and bits
10, 6, and 2 in DMABCR, by the DTC.
Bit 2
WE1A
0
1
Description
Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled
(Initial value)
Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled
Rev.6.00 Sep. 27, 2007 Page 251 of 1268
REJ09B0220-0600