D12320VF25IV Datasheet, PDF (1069/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix A Instruction Set
Figure A.1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals
during execution of the above instruction with an 8-bit bus, using three-state access with no wait
states.
φ
Address bus
RD
HWR, LWR
High
R:W 2nd
Fetching
3rd byte
of instruction
Fetching
4th byte
of instruction
Internal
operation
R:W EA
Fetching
1st byte of
instruction at
jump address
Fetching
2nd byte of
instruction at
jump address
Figure A.1 Address Bus, RD, HWR, and LWR Timing
(8-Bit Bus, Three-State Access, No Wait States)
Rev.6.00 Sep. 27, 2007 Page 1037 of 1268
REJ09B0220-0600