D12320VF25IV Datasheet, PDF (467/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Pin
PF0/BREQ
Section 9 I/O Ports
Selection Method and Pin Functions
The pin function is switched as shown below according to the combination of
the operating mode, and bits BRLE and PF0DDR.
Operating
Mode
Modes 4 to 6
Mode 7
BRLE
0
1
—
PF0DDR
Pin function
0
PF0
input pin
1
PF0
output pin
—
BREQ
input pin
0
PF0
input pin
1
PF0
output pin
9.14 Port G
9.14.1 Overview
Port G is a 5-bit I/O port. Port G pins also function as bus control signal output pins (CS₀ to CS₃,
and CAS^*). Enabling or disabling of CS₁ to CS₃ output can be changed by a setting in PFCR2.
Figure 9.23 shows the port G pin configuration.
Note: * CAS is not supported in the H8S/2321.
Port G
Port G pins
PG₄ / CS₀
PG₃ / CS₁
PG₂ / CS₂
PG₁ / CS₃
PG₀ / CAS*
Pin functions in modes 4 to 6
PG₄ (input) / CS₀ (output)
PG₃ (I/O) / CS₁ (output)
PG₂ (I/O) / CS₂ (output)
PG₁ (I/O) / CS₃ (output)
PG₀ (I/O) / CAS* (output)
Pin functions in mode 7
PG₄ (I/O)
PG₃ (I/O)
PG₂ (I/O)
PG₁ (I/O)
PG₀ (I/O)
Note: * CAS is not supported in the H8S/2321.
Figure 9.23 Port G Pin Functions
Rev.6.00 Sep. 27, 2007 Page 435 of 1268
REJ09B0220-0600