D12320VF25IV Datasheet, PDF (230/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.6 DMAC Single Address Mode and DRAM Interface
(Not supported in the H8S/2321)
When burst mode is selected with the DRAM interface, the DACK output timing can be selected
with the DDS bit. When DRAM space is accessed in DMAC single address mode at the same
time, this bit selects whether or not burst access is to be performed.
6.6.1 When DDS = 1
Burst access is performed by determining the address only, irrespective of the bus master. The
DACK output goes low from the T_C1 state in the case of the DRAM interface.
Figure 6.28 shows the DACK output timing for the DRAM interface when DDS = 1.
φ
A₂₃ to A₀
T_p
T_r
T_c1
T_c2
Row
Column
CSn (RAS)
CAS (UCAS)
LCAS (LCAS)
Read
HWR (WE)
D₁₅ to D₀
Write
HWR (WE)
D₁₅ to D₀
DACK
Note: n = 2 to 5
Figure 6.28 DACK Output Timing when DDS = 1 (Example of DRAM Access)
Rev.6.00 Sep. 27, 2007 Page 198 of 1268
REJ09B0220-0600