D12320VF25IV Datasheet, PDF (383/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 I/O Ports
Port Description
Pins
Mode 4^*1
Mode 5^*1
Mode 6
Mode 7
Port F • 8-bit I/O
port
Port G • 5-bit I/O
port
PF1/BACK
PF0/BREQ
PG4/CS0
When BRLE = 0 (after reset): I/O port
I/O ports
When BRLE = 1: BREQ input, BACK output
When DDR = 0^*3: input port
I/O ports
When DDR = 1^*4: CS0 output
PG3/CS1
When DDR = 0 (after reset): input port
When CS167E = 0 and DDR = 1: output port
When CS167E = 1 and DDR = 1: CS1
output
PG2/CS2
When DDR = 0 (after reset): input port
When CS25E = 0 and DDR = 1: output port
When CS25E = 1 and DDR = 1: CS2 output
PG1/CS3
When DDR = 0 (after reset): input port
When CS25E = 0 and DDR = 1: output port
When CS25E = 1 and DDR = 1: CS3 output
PG0/CAS^*2
DRAM space set: CAS output
Otherwise (after reset): I/O port
Notes: 1. Only modes 4 and 5 are provided in the ROMless version.
2. The DACK1, DACK0, TEND1, DREQ1, TEND0, DREQ0 and LCAS are not supported
in the H8S/2321.
3. After a reset in mode 6.
4. After a reset in mode 4 or 5.
Rev.6.00 Sep. 27, 2007 Page 351 of 1268
REJ09B0220-0600