D12320VF25IV Datasheet, PDF (264/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short
address mode or full address mode.
In short address mode, channels 0A and 0B can be used as independent channels.
Bit 14
FAE0
0
1
Description
Short address mode
Full address mode
(Initial value)
Bit 13—Single Address Enable 1 (SAE1): Specifies whether channel 1B is to be used for
transfer in dual address mode or single address mode.
This bit is invalid in full address mode.
Bit 13
SAE1
0
1
Description
Transfer in dual address mode
Transfer in single address mode
(Initial value)
Bit 12—Single Address Enable 0 (SAE0): Specifies whether channel 0B is to be used for
transfer in dual address mode or single address mode.
This bit is invalid in full address mode.
Bit 12
SAE0
0
1
Description
Transfer in dual address mode
Transfer in single address mode
(Initial value)
Bits 11 to 8—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when
DMA transfer is performed, of the internal interrupt source selected by the data transfer factor
setting.
When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor
setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal
interrupt source selected by the data transfer factor setting does not issue an interrupt request to the
CPU or DTC.
Rev.6.00 Sep. 27, 2007 Page 232 of 1268
REJ09B0220-0600