D12320VF25IV Datasheet, PDF (114/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 MCU Operating Modes
Bit 1—IRQ Port Switching Select (IRQPAS): Selects switching of input pins for IRQ₄ to IRQ₇.
IRQ₄ to IRQ₇ input is always performed from one of the ports.
Bit 1
IRQPAS
0
1
Description
PA4 to PA7 are used for IRQ4 to IRQ7 input
P50 to P53 are used for IRQ4 to IRQ7 input
(Initial value)
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME
0
1
Description
On-chip RAM is disabled
On-chip RAM is enabled
(Initial value)
3.2.3 System Control Register 2 (SYSCR2) (F-ZTAT Version Only)
Bit
:
7
6
5
—
—
—
Initial value :
0
0
0
R/W
:—
—
—
Note: * R/W in the H8S/2329B F-ZTAT.
4
3
2
— FLSHE —
0
0
0
—
R/W
—
1
0
—
—
0
0
— — (R/W)^*
SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control.
SYSCR2 is initialized to H'00 by a reset, and in hardware standby mode.
Bits 7 to 4—Reserved: These bits are always read as 0, and cannot be modified.
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). For details, see section 19,
ROM.
Rev.6.00 Sep. 27, 2007 Page 82 of 1268
REJ09B0220-0600