D12320VF25IV Datasheet, PDF (304/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
For setting details, see section 7.3.4, DMA Control Register (DMACR).
Figure 7.12 shows an example of the setting procedure for normal mode.
Normal mode setting
Set DMABCRH
[1]
Set transfer source and
transfer destination
[2]
addresses
Set number of transfers [3]
Set DMACR
[4]
Read DMABCRL
[5]
Set DMABCRL
[6]
[1] Set each bit in DMABCRH.
• Set the FAE bit to 1 to select full address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
[2] Set the transfer source address in MARA, and
the transfer destination address in MARB.
[3] Set the number of transfers in ETCRA.
[4] Set each bit in DMACRA and DMACRB.
• Set the transfer data size with the DTSZ bit.
• Specify whether MARA is to be incremented,
decremented, or fixed, with the SAID and
SAIDE bits.
• Clear the BLKE bit to 0 to select normal
mode.
• Specify whether MARB is to be incremented,
decremented, or fixed, with the DAID and
DAIDE bits.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read DTE = 0 and DTME = 0 in DMABCRL.
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts with the DTIE bit.
• Set both the DTME bit and the DTE bit to 1 to
enable transfer.
Normal mode
Figure 7.12 Example of Normal Mode Setting Procedure
Rev.6.00 Sep. 27, 2007 Page 272 of 1268
REJ09B0220-0600