D12320VF25IV Datasheet, PDF (308/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
Address TA
Address BA
Block area
Transfer
Consecutive transfer
of M bytes or words
is performed in
response to one
request
1st block
2nd block
Address T_B
Nth block
Address B_B
Legend:
Address TA = LA
Address TB = LB
Address BA = LA + SAIDE · (–1)^SAID · (2^DTSZ · (N–1))
Address BB = LB + DAIDE · (–1)^DAID · (2^DTSZ · (M·N–1))
Where : LA = Value set in MARA
LB = Value set in MARB
N = Value set in ETCRB
M = Value set in ETCRAH and ETCRAL
Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1)
ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a
single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00.
ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register
for which a block designation has been given by the BLKDIR bit in DMACRA is restored in
accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.
Rev.6.00 Sep. 27, 2007 Page 276 of 1268
REJ09B0220-0600