D12320VF25IV Datasheet, PDF (188/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
Bit 3
BRSTS0
0
1
Description
Max. 4 words in burst access
Max. 8 words in burst access
(Initial value)
Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): These bits select the memory interface for
areas 2 to 5 in advanced mode.
When DRAM space is selected, the relevant area is designated as a DRAM interface area. In the
H8S/2321 these bits are reserved and should only be written with 0.
Bit 2
RMTS2
0
1
Bit 1
RMTS1
0
1
—
Bit 0
RMTS0
0
1
0
1
—
Description
Area 5
Normal space
Normal space
Normal space
DRAM space
—
Area 4
Area 3
Area 2
DRAM space
DRAM space
The LCAS pin is used for the LCAS signal on the 2-CAS DRAM interface. If it is wished to use
BREQO output and WAIT input when using the LCAS signal, it is possible to switch to the P5₃
pin by means of the BREQOPS bit in PFCR2. For details, see section 9.6, Port 5 and section 9.13,
Port F.
Note:
This note applies to the H8S/2323 only. If all areas selected as DRAM space are 8-bit
space, the PF₂ pin can be used as an I/O port, or as the BREQ0 or WAIT pin. However, if
PF₂ is used as the WAIT pin on the H8S/2323 only, normal space other than DRAM space
should be designated as 16-bit bus space. The RAS down mode cannot be used in this
case. Sample settings are shown below.
RMTS2
0
RMTS1
0
1
RMTS0
0
1
0
1
Area 5
Area 4
Normal space
Normal space
(16-bit bus)
Normal space
(16-bit bus)
DRAM space
(8-bit bus)
Area 3
Area 2
DRAM space
(8-bit bus)
DRAM space
(8-bit bus)
Rev.6.00 Sep. 27, 2007 Page 156 of 1268
REJ09B0220-0600