D12320VF25IV Datasheet, PDF (250/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
⎯ External request
⎯ Auto-request
• Module stop mode can be set
⎯ The initial setting enables DMAC registers to be accessed. DMAC operation is halted by
setting module stop mode
7.1.2 Block Diagram
A block diagram of the DMAC is shown in figure 7.1.
Internal interrupts
TGI0A
TGI1A
TGI2A
TGI3A
TGI4A
TGI5A
TXI0
RXI0
TXI1
RXI1
ADI
External pins
DREQ0
DREQ1
TEND0
TEND1
DACK0
DACK1
Interrupt signals
DEND0A
DEND0B
DEND1A
DEND1B
Internal address bus
Control logic
DMAWER
DMATCR
DMACR0A
DMACR0B
DMACR1A
DMACR1B
DMABCR
Data buffer
Address buffer
Processor
MAR0A
IOAR0A
ETCR0A
MAR0B
IOAR0B
ETCR0B
MAR1A
IOAR1A
ETCR1A
MAR1B
IOAR1B
ETCR1B
Internal data bus
Legend:
DMAWER: DMA write enable register
DMATCR: DMA terminal control register
DMABCR: DMA band control register (for all channels)
DMACR: DMA control register
MAR:
Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
Figure 7.1 Block Diagram of DMAC
Rev.6.00 Sep. 27, 2007 Page 218 of 1268
REJ09B0220-0600