D12320VF25IV Datasheet, PDF (952/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 21 Power-Down Modes
Table 21.1 Operating Modes
Operating Transition Clearing
Mode
Condition Condition Oscillator
CPU
Registers
Modules
Registers I/O Ports
High speed Control
mode
register
Functions High Function
speed
High Function High speed
speed
Medium- Control
speed mode register
Functions Medium Function
speed
High/ Function
medium
speed ^*1
High speed
Sleep mode Instruction Interrupt
Functions Halted Retained
High Function High speed
speed
Module stop Control
mode
register
Functions
High/ Function
medium
speed
Halted Retained/ Retained
reset ^*2
Software
standby
mode
Instruction External
interrupt
Halted
Halted Retained
Halted Retained/ Retained
reset ^*2
Hardware Pin
standby
mode
Halted
Halted Undefined Halted Reset
High
impedance
Notes: 1. The bus master operates on the medium-speed clock, and other on-chip supporting
modules on the high-speed clock.
2. Some SCI registers and the A/D converter are reset, and other on-chip supporting
modules retain their states.
21.1.1 Register Configuration
Power-down modes are controlled by the SBYCR, SCKCR, and MSTPCR registers. Table 21.2
summarizes these registers.
Table 21.2 Power-Down Mode Registers
Name
Abbreviation
Standby control register
SBYCR
System clock control register
SCKCR
Module stop control register H MSTPCRH
Module stop control register L MSTPCRL
Note: * Lower 16 bits of the address.
R/W
R/W
R/W
R/W
R/W
Initial Value
H'08
H'00
H'3F
H'FF
Address^*
H'FF38
H'FF3A
H'FF3C
H'FF3D
Rev.6.00 Sep. 27, 2007 Page 920 of 1268
REJ09B0220-0600