D12320VF25IV Datasheet, PDF (10/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Item
Page
1.3.1 Pin Arrangement 15
Figure 1.8
HD64F2329B Pin
Arrangement (FP-
128B: Top View)
1.3.3 Pin Functions 26
Table 1.3 Pin Functions
6.3.5 Chip Select
169
Signals
Revision (See Manual for Details)
Figure added
Table amended
Operating
MD2 MD1 MD0 Mode
0
0
1
—
1
0
Mode 2^*1
1
Mode 3^*1
1
0
0
Mode 4^*2
1
Mode 5^*2
1
0
Mode 6
1
Mode 7
Description amended
Enabling or disabling of the CSn signal is performed by setting
the data direction register (DDR) for the port corresponding to
the particular CSn pin and either the CS167 enable bit
(CS167E) or the CS25 enable bit (CS25E).
In ROM-disabled expansion mode, the CS0 pin is placed in the
output state after a power-on reset. Pins CS1 to CS7 are placed
in the input state after a power-on reset, so the corresponding
DDR bits, and CS167E or CS25E, should be set to 1 when
outputting signals CS1 to CS7.
In ROM-enabled expansion mode, pins CS0 to CS7 are all
placed in the input state after a power-on reset, so the
corresponding DDR bits, and CS167E or CS25E, should be set
to 1 when outputting signals CS0 to CS7.
Rev.6.00 Sep. 27, 2007 Page viii of xxx
REJ09B0220-0600