D12320VF25IV Datasheet, PDF (33/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 1 Overview
Section 1 Overview
1.1 Overview
The H8S/2329 Group and H8S/2328 Group are series of microcomputers (MCUs: microcomputer
units), built around the H8S/2000 CPU, employing Renesas’ proprietary architecture, and
equipped with supporting functions on-chip.
The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general
registers and a concise, optimized instruction set designed for high-speed operation, and can
address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300
and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,
H8/300L, or H8/300H Series.
On-chip supporting functions required for system configuration include DMA controller
(DMAC)*¹ and data transfer controller (DTC) bus masters, ROM and RAM, a 16-bit timer-pulse
unit (TPU), programmable pulse generator (PPG), 8-bit timer, watchdog timer (WDT), serial
communication interface (SCI), A/D converter, D/A converter, and I/O ports.
A high-functionality bus controller is also provided, enabling fast and easy connection of DRAM
and other kinds of memory.
Single-power-supply flash memory (F-ZTAT™*²) and mask ROM versions are available,
providing a quick and flexible response to conditions from ramp-up through full-scale volume
production, even for applications with frequently changing specifications. ROM is connected to
the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state.
Instruction fetching is thus speeded up, and processing speed increased.
The features of the H8S/2329 Group is shown in table 1.1.
Notes: 1. The DMAC is not supported in the H8S/2321.
2. F-ZTAT is a trademark of Renesas Technology Corp.
Rev.6.00 Sep. 27, 2007 Page 1 of 1268
REJ09B0220-0600