D12320VF25IV Datasheet, PDF (1224/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
TCNT—Timer Counter
Bit
:7
6
5
H'FFBC (W), H'FFBD (R)
4
3
2
1
WDT
0
Initial value : 0
Read/Write : R/W
0
0
R/W R/W
0
0
0
R/W R/W R/W
0
0
R/W R/W
RSTCSR—Reset Control/Status Register
Bit
:
7
6
5
WOVF RSTE —
Initial value :
0
0
0
Read/Write : _{R/(W)* R/W R/W}
H'FFBE (W), H'FFBF (R)
4
3
2
1
—
—
—
—
1
1
1
1
—
—
—
—
WDT
0
—
1
—
Reserved
This bit should be written with 0
Reset Enable
0 Reset signal is not generated if TCNT overflows*
1 Reset signal is generated if TCNT overflows
Note: * The modules in the H8S/2329 and H8S/2328 Groups are
not reset, but TCNT and TCSR in WDT are reset.
Watchdog Timer Overflow Flag
0 [Clearing condition]
When 0 is written to WOVF after reading RSTCSR when WOVF = 1
1 [Setting condition]
When TCNT overflows (changes from H'FF to H'00) during watchdog
timer operation
Note: * Can only be written with 0 for flag clearing.
The method for writing to RSTCSR is different from that for general registers to prevent accidental
overwriting. For details, see section 13.2.4, Notes on Register Access.
Rev.6.00 Sep. 27, 2007 Page 1192 of 1268
REJ09B0220-0600