D12320VF25IV Datasheet, PDF (299/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
7.5.5 Single Address Mode
Single address mode can only be specified for channel B. This mode can be specified by setting
the SAE bit in DMABCR to 1 in short address mode.
One address is specified by MAR, and the other is set automatically to the data transfer
acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR.
Table 7.9 summarizes register functions in single address mode.
Table 7.9 Register Functions in Single Address Mode
Function
Register
23
MAR
DACK pin
15
ETCR
DTDIR = 0 DTDIR = 1 Initial Setting
Operation
0 Source
address
register
Destination Start address of ^*
address transfer destination
register or transfer source
Write
strobe
Read
strobe
(Set automatically Strobe for external
by SAE bit; IOAR is device
invalid)
0 Transfer counter
Number of transfers ^*
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer register
DTDIR: Data transfer direction bit
DACK: Data transfer acknowledge
Note: * See the operation descriptions in sections 7.5.2, Sequential Mode, 7.5.3, Idle Mode, and
7.5.4, Repeat Mode.
MAR specifies the start address of the transfer source or transfer destination as 24 bits.
IOAR is invalid; in its place the strobe for external devices (DACK) is output.
Rev.6.00 Sep. 27, 2007 Page 267 of 1268
REJ09B0220-0600